Semiconductor manufacturing steps for forming a semiconductor device, including a field effect transistor (FET) device and a fin field effect transistor (finFET) device, may include forming trench regions in a contact-level dielectric layer of the device, and forming contacts in the trench regions. The contacts may form electrical connections between various components of the semiconductor device. In one example, these connections may be local interconnects. There may be a direct or indirect interface between the contacts and a source/drain region of the semiconductor device.
As integrated circuits become increasingly complex, the need for increased packaging density, reduced device parasitics, and low resistivity interconnects increases. Silicide local interconnects have been utilized to reduce pitch requirements, device parasitic capacitance, and interconnect resistances.
A reduction in resistance and capacitance at an interface between a silicide layer and a source/drain region may improve device performance. For example, a relatively small interface area may reduce capacitance but increase resistance. Conversely, a relatively large interface area may reduce resistance but increase capacitance. Therefore, under the prior art, a tradeoff exists between resistance and capacitance; However, a limit to performance improvements from adjusting interface area exists resulting in a need for an improved structure and method of forming semiconductor devices to decrease both resistance and capacitance at an interface between the silicide layer and the source/drain region.